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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. cs4361 20-pin, 24-bit, 192 khz, 6-channel d/a converter features z multi-bit delta-sigma modulator z 24-bit conversion z automatically detects sample rates up to 192 khz. z 105 db dynamic range z -95 db thd+n z low clock jitter sensitivity z +3.3 v or +5 v core power z +1.8 v to +5 v interface power z filtered line level outputs z on-chip digital de-emphasis z popguard ? technology z mute output control z small 20-pin tssop package description the cs4361 is a complete 6-channel digital-to-analog output system including inte rpolation, multi-bit d/a conversion, and output analog filtering in a small 20-pin package. the cs4361 supports all major audio data interface formats. the cs4361 is based on a fourth order, multi-bit, delta- sigma modulator with a linear analog low-pass filter. this device also includes auto-speed mode detection using both sample rate and master clock ratio as a method of auto-selecting sampling rates between 2 khz and 216 khz. the cs4361 contains on-chip digital de-emphasis, oper- ates from a single +3.3 v or +5 v power supply with separate built-in level shifter for the digital interface, and requires minimal support circuitry. these features are ideal for dvd players & recorders, digital televisions, home theater and set top box products, and automotive audio systems. ordering in formation see page 20 i internal voltage reference +5 volt-tolerant reset auto-speed detecting pcm serial interface level translator mode control analog & digital core supply (3.3 v to 5 v) single-ended outputs (six channels) 6 pcm serial audio input digital filters switch-cap dac and analog filters multi-bit ? modulators external mute control mute control serial audio port & control supply (1.8 v to 5 v) 6 digital de-emphasis jan ?05 ds672a2
cs4361 2 ds672a2 table 1. revision history release date changes a1 january 2005 initial release a2 january 2005 correction to pdf file size. contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pe rtaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this in formation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, ci rrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage ("critical applications"). ci rrus products are not designed, authorized or warranted for use in aircraft systems, milita ry applications, product s surgically implanted into the body, automotive safety or security devices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, includ- ing the implied warranties of merchantability and fitness fo r particular purpose, with regard to any cirrus product that is used in such a manner. if the custo mer or customer's custo mer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnif y cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys' fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.
cs4361 ds672a2 3 table of contents 1. pin descriptions .......................................................................................................... ...... 4 2. characteristics and specifications ........................................................................ 5 specified operating conditions ................................................................................................ 5 absolute maximum ratings ................................. ..................................................................... 5 dac analog characteristics ..................................................................................................... 6 dac analog characteristics - all modes .................................................................................. 6 combined interpolation & on-chi p analog filter response ..................................................... 7 digital input charac teristics .................................................................................................. .... 8 power & thermal characteristics ........................ ..................................................................... 8 switching characteristics - serial audio interf ace .................................................................... 9 3. typical connection diagram ..................................................................................... 11 4. applications .............................................................................................................. ....... 12 4.1 master clock .............................................................................................................. ...... 12 4.2 serial clock .............................................................................................................. ....... 12 4.2.1 external serial clock mode ................................................................................. 12 4.2.2 internal serial clock mode ............... ................................................................... 13 4.3 de-emphasis ............................................................................................................... .... 15 4.4 mode select ............................................................................................................... ...... 15 4.5 initialization and power-do wn ......................................................................................... 15 4.6 output transient control ................................................................................................. 1 7 4.6.1 power-up ............................................................................................................. 17 4.6.2 power-down ........................................................................................................ 17 4.7 grounding and power supply decoupling ....................................................................... 17 4.8 analog output and filtering ............................................................................................. 17 4.9 mute control .............................................................................................................. ...... 18 5. parameter definitions .................................................................................................. 19 6. ordering information .............................................................................................. 20 7. package dimensions ...................................................................................................... 20 8. appendix ............ ................ ................ ................ ................. ................ ................ ............ 21
cs4361 4 ds672a2 1. pin descriptions pin name # pin description sdin1 sdin2 sdin3 2 3 4 serial audio data input ( input ) - input for two?s complement serial audio data. dem /sclk 5 de-emphasis/external serial clock input ( input ) - used for de-emphasis filter control or exter- nal serial clock input. lrck 6 left right clock ( input ) - determines which channel, left or right, is currentl y active on the serial audio data line. mclk 7 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vq 11 quiescent voltage ( output ) - filter connection for internal quiescent voltage. filt+ 10 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. aout1 aout2 aout3 aout4 aout5 aout6 19 18 17 16 13 12 analog output ( output ) - the full scale analog output level is specified in the analog charac- teristics specif ication table. gnd 14 ground ( input ) - ground reference. va 15 analog power ( input ) - positive power for the analog and core digital sections. vl 1 interface power ( input ) - positive power for the digita l interface level shifters. rst 8 reset ( input ) - applies reset to the internal circuitry when low. mutec 20 mute control ( output ) - control signal for optional external muting circuitry. mode 9 mode control ( input ) - selects operational modes (see table 3). vl mutec sdin1 aout1 sdin2 aout2 sdin3 aout3 dem /sclk aout4 lrck va mclk gnd rst aout5 mode aout6 filt+ vq 1 2 3 4 5 16 17 18 19 20 6 7 8 9 10 11 12 13 14 15
cs4361 ds672a2 5 2.characteristics and specifications all min/max characteristics and specifications are guaran teed over the specified operat ing conditions. typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltage and t a = 25 c. specified operat ing conditions agnd = 0 v; all voltages with respect to ground. absolute maximum ratings agnd = 0 v; all voltages with respect to ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min nom max units dc power supply va va vl 4.75 3.0 1.7 5.0 3.3 3.3 5.25 3.6 5.25 v v specified temperature range -czz -dzz t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply va vl -0.3 -0.3 6.0 va v v input current, any pin except supplies i in -10ma digital input voltage (pin 8, rst )v ind -0.3 va+0.4 v digital input voltage (all other digital pins) v ind -0.3 vl+0.4 v ambient operating temperature (power applied) t op -55 125 c storage temperature t stg -65 150 c
cs4361 6 ds672a2 dac analog characteristics full-scale output sine wave, 997 hz (note 1), fs = 48/96/192 khz; test load r l = 3 k ? , c l = 10 pf (see figure 1). measurement bandwidth is 10 hz to 20 khz, unless othe rwise specified. note: 1. one-half lsb of triangular pdf dither added to data. dac analog character istics - all modes parameter 5v nom 3.3v nom min typ max min typ max unit dynamic performance for cs4361-czz (-10 to 70c) dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 99 96 90 87 105 102 96 93 - - - - 97 94 90 87 103 100 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -95 -82 -42 -93 -73 -33 -89 -76 -36 -87 -67 -27 - - - - - - -95 -80 -40 -93 -73 -33 -89 -74 -34 -87 -67 -27 db db db db db db dynamic performance for CS4361-DZZ (-40 to 85c) dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 95 92 86 83 105 102 96 93 - - - - 93 90 86 83 103 100 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -95 -82 -42 -93 -73 -33 -85 -72 -32 -83 -63 -23 - - - - - - -95 -80 -40 -93 -73 -33 -85 -70 -30 -83 -63 -23 db db db db db db parameter symbol min typ max unit interchannel isolation (1 khz) - 100 - db dc accuracy interchannel gain mismatch - 0.1 0.25 db gain drift - 100 - ppm/c analog output full scale output voltage 0.60?va 0.65?va 0.70?va vpp quiescent voltage v q - 0.5?va - vdc max dc current draw from an aout pin i outmax -10- a max current draw from vq i qmax - 100 - a min ac-load resistance (see figure 2 on page 8) r l -3-k ? max load capacitance (see figure 2) c l - 100 - pf output impedance z out - 100 - ?
cs4361 ds672a2 7 combined interpolation & on-c hip analog filter response the filter characteristics have been normalized to the sample rate (fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by fs. (see note 5) notes: 2. response is clock-dependent and will scale with fs. 3. for single speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. for quad speed mode, the measurement bandwidth is 0.7 fs to 1 fs. 4. de-emphasis is available only in single speed mode. 5. amplitude vs. frequency plots of this data are available in ?appendix? on page 21. parameter symbol min typ max unit combined digital and on-chip analog filter response single speed mode passband (note 2) to -0.05 db corner to -3 db corner 0 0 - - .4780 .4996 fs fs frequency response 10 hz to 20 khz -.01 - +.08 db stopband .5465 - - fs stopband attenuation (note 3) 50 - - db group delay tgd - 10/fs - s de-emphasis error (note 4) fs = 44.1 khz - - +.05/-.25 db combined digital and on-chip analog filter response double speed mode passband (note 2) to -0.1 db corner to -3 db corner 0 0 - - .4650 .4982 fs fs frequency response 10 hz to 20 khz -.05 - +.2 db stopband .5770 - - fs stopband attenuation (note 3) 55 - - db group delay tgd - 5/fs - s combined digital and on-chip analog filter response quad speed mode passband (note 2) to -0.1 db corner to -3 db corner 0 0 - - 0.397 0.476 fs fs frequency response 10 hz to 20 khz 0 - +0.00004 db stopband 0.7 - - fs stopband attenuation (note 3) 51 - - db group delay tgd - 2.5/fs - s
cs4361 8 ds672a2 digital input characteristics 6. rst pin has an input threshold re lative to vl but is va tolerant. 7. i in for lrck is 20 a max. power & thermal characteristics 8. current consumption increases with increasing fs and increasing mclk. typ and max values are based on highest fs and highest mclk. curr ent variance between speed modes is small. 9. power down mode is defined when a ll clock and data lines are held static. 10. valid with the recommended capacitor values on vq and filt+ as shown in the typical connection diagram in section 3. parameters symbol min typ max units high-level input voltage -all input pins except rst (% of vl) v ih 70% - - v low-level input voltage -all input pins except rst (% of vl) v il --30%v high-level input voltage -rst pin (note 6) (% of vl) v ih 90% - - v low-level input voltage -rst pin (% of vl) v il --10%v input leakage current (note 7) i in --10 a input capacitance - 8 - pf 5v nom 3.3v nom parameters symbol min typ max min typ max units power supplies power supply current normal operation (note 8) power-down state (note 9) i a i l i a i l - - - - 66 0.1 300 26 90 1 - - - - - - 48 0.1 180 24 63 1 - - ma ma a a power dissipation normal operation power-down state (note 9) - - 331 1.63 455 - - - 159 0.67 211 - mw mw package thermal resistance ja -72- -72-c/watt power supply rejection ratio (note 10) (1 khz) (60 hz) psrr - - 60 40 - - - - 60 40 - - db db aoutx agnd 3.3 f v out r l c l figure 1. equivalent output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 figure 2. maximum loading
cs4361 ds672a2 9 switching characteristics - serial audio interface notes: 11. not all sample rates are supported for all cl ock ratios. see table ?common clock frequencies? on page 12 for supported ratios and frequencies. 12. in internal sclk mode, the duty cycle must be 50% 1/2 mclk period. 13. the sclk / lrck ratio may be either 32, 48, 64, or 72. this ratio depends on data format and mclk/lrck ratio. (see figures 7-10) parameters symbol min typ max units mclk frequency 0.512 - 50 mhz mclk duty cycle 45 - 55 % input sample rate all mclk/lrck ratios combined (note 11) 256x, 384x, 1024x 256x, 384x 512x, 768x 1152x 128x, 192x 64x, 96x 128x, 192x fs 2 2 84 42 30 50 100 168 216 54 134 67 34 108 216 216 khz khz khz khz khz khz khz khz external sclk mode lrck duty cycle (external sclk only) 45 50 55 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk duty cycle 45 50 55 % sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdin valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdin hold time t sdh 20 - - ns internal sclk mode lrck duty cycle (internal sclk only) (note 12) - 50 - % sclk period (note 13) t sclkw --ns sclk rising to lrck edge t sclkr -- s sdin valid to sclk rising setup time t sdlrs --ns sclk rising to sdin hold time mclk / lrck =1152, 1024, 512, 256, 128, or 64 t sdh --ns sclk rising to sdin hold time mclk / lrck = 768, 384, 192, or 96 t sdh --ns 10 9 sclk ---------------- - tsclkw 2 ------------------ 10 9 512 () fs --------------------- -10 + 10 9 512 () fs --------------------- -15 + 10 9 384 () fs --------------------- -15 +
cs4361 10 ds672a2 sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 3. external serial mode input timing sdata *internal sclk lrck sclkw t sdlrs t sdh t sclkr t figure 4. internal serial mode input timing * the sclk pulses shown are internal to the cs4361. sdata lrck mclk *internal sclk 1 n 2 n figure 5. internal serial clock generation * the sclk pulses shown are internal to the cs4361. n equals mclk divided by sclk
cs4361 ds672a2 11 3. typical conn ection diagram dem/sclk 14 audio data processor external clock mclk gnd cs4361 sdin1 lrck vl aout1 6 2 5 7 1 0.1 f + 1f 19 audio output +3.3 v to +5 v 3.3 f 10 k ? c 470 ? + r+470 c= 4 fs(r 470) r ext ext ext + 0.1 f 33 + f 10 vq filt+ 11 note* note* = this circuitry is intended for applications where the cs4361 connects directly to an unbalanced output of the design. for internal routing applications please see the dac analog output characteristics for loading limitations. for best 20 khz response sdin2 3 sdin3 4 20 mutec aout2 18 aout3 17 aout4 16 aout5 13 aout6 12 optional muting circuit rst 8 controler mode 9 +1.8 v to +5 v va 15 vl gnd lrck lj rj16 rj24 i 2 s mclk f *3.3 f *10 *popguard ramp can be adjusted by selecting this capacitor value to be 3.3 f to give 250 ms ramp time or 10 f to give a 420 ms ramp time. or figure 6. recommended connection diagram
cs4361 12 ds672a2 4.applications the cs4361 accepts data at standard audio sample rate s including 48, 44.1 and 32 khz in ssm, 96, 88.2 and 64 khz in dsm, and 192, 176.4 and 128 khz in qsm. audio data is input via the serial data input pin (sdin). the left/right clock (lrck) de termines which channel is cu rrently being input on sdin, and the optional serial clock (sclk) clocks audio data into the input data buffer. 4.1 master clock mclk/lrck must be an integer ratio as shown in table 2 . the lrck frequency is equal to fs, the frequency at which words for each channel are input to the device. the mclk-to-lrck frequency ratio and speed mode is de- tected automatically during the initializat ion sequence by counting the number of mclk transitions during a single lrck period and by detecting the absolute speed of mclk. in ternal dividers are set to generate the proper clocks. table 2 illustrates several standard audi o sample rates and the required mclk and lrck frequen cies. please note there is no required phase relationship, but mclk, lrck, and sclk must be synchronous. table 2. common clock frequencies 4.2 serial clock the serial clock controls the shifting of data into the i nput data buffers. the cs4361 supports both external and in- ternal serial clock generation modes. refer to figures 7-10 for data formats. 4.2.1 external serial clock mode the cs4361 will enter the exter nal serial clock mode when 16 low-to -high transitions ar e detected on the dem /sclk pin during any phase of the lrck period. when this mode is enabled, the internal serial clock mode and de-em phasis filter cannot be accesse d. the cs4361 will switch to in ternal serial clock mode if no low-to-high transitions are detected on the dem /sclk pin for two consecutiv e frames of lrck. refer to figure 12. lrck (khz) mclk (mhz) 64x 96x 128x 192x 256x 384x 512x 768x 1024x 1152x 32 - --- 8.1920 12.2880 - - 32.7680 36.8640 44.1 - --- 11.2896 16.9344 22.5792 33.8680 45.1580 - 48 - --- 12.2880 18.4320 24.5760 36.8640 49.1520 - 64 - - 8.1920 12.2880 - - 32.7680 49.1520 - - 88.2 - - 11.2896 16.9344 22.5792 33.8680 - - - - 96 - - 12.2880 18.4320 24.5760 36.8640 - - - - 128 8.1920 12.2880 - - 32.7680 49.1520 - - - - 176.4 11.2896 16.9344 22.5792 33.8680 - - - - - - 192 12.2880 18.4320 24.5760 36.8640 - - - - - - mode qsm dsm ssm
cs4361 ds672a2 13 4.2.2 internal serial clock mode in the internal serial clock mode, th e serial clock is internally derived and synchronous with mclk and lrck. the sclk/lrck frequency ratio is either 32, 48, 64, or 72 depending upon data format. operation in this mode is identical to operation with an exte rnal serial clock synchr onized with lrck. this mo de allows access to the digital de-emphasis function. refer to figures 7 - 12 for details. lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i 2 s, 16-bit data and int sclk = 32 fs if mclk/lrck = 1024, 512, 256, 128, or 64 i 2 s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 i 2 s, up to 24-bit data and int sclk = 72 fs if mclk/lrck = 1152 i 2 s, up to 24-bit data data valid on rising edge of sclk figure 7. cs4361 data format (i 2 s) lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode left justified, up to 24-bit data int sclk = 64 fs if mclk/lrck = 1024, 512, 256, 128, or 64 int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 int sclk = 72 fs if mclk/lrck = 1152 left justified, up to 24-bit data data valid on rising edge of sclk figure 8. cs4361 data format (left justified)
cs4361 14 ds672a2 lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel internal sclk mode external sclk mode right justified, 24-bit data int sclk = 64 fs if mclk/lrck = 1024, 512, 256, 128, or 64 int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 int sclk = 72 fs if mclk/lrck = 1152 right justified, 24-bit data data valid on rising edge of sclk sclk must have at least 48 cycles per lrck period figure 9. cs4361 data format (right justified 24) lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks internal sclk mode external sclk mode right justified, 16-bit data int sclk = 32 fs if mclk/lrck = 1024, 512, 256, 128, or 64 int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 int sclk = 72 fs if mclk/lrck = 1152 right justified, 16-bit data data valid on rising edge of sclk sclk must have at least 32 cycles per lrck period figure 10. cs4361 data format (right justified 16)
cs4361 ds672a2 15 4.3 de-emphasis the cs4361 includes on-chip digital de-emphasis. figure 11 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency response of the de-emphasis curve will scale proporti onally with changes in sample rate, fs. the de-emphasis filter is active (inactive) if the dem /sclk pin is low (high) for fi ve consecutive falling edges of lrck. this function is available only in the internal serial clock mo de when lrck < 50 khz. 4.4 mode select mode selection is determined by the mode select pin. th e value of this pin is locked 1024 lrck cycles after rst is released. this pin requires a specific connection to supply, ground, mclk, or lrck as outlined in table 3. . table 3. mode pin settings 4.5 initialization and power-down the initialization and power-down sequen ce flow chart is shown in figure 12. the cs4361 enters the power-down state upon initial power-up. the interpolation filters and de lta-sigma modulators are reset, and the internal voltage reference, multi-bit digital-to-analog converters, and switched-capacitor low-pass filters are powered down. the de- vice will remain in the po wer-down mode until rst is released and mclk and lrck are present. once mclk and lrck are detected, mclk occurrences are counted over one lrck period to determine the mclk/lrck frequency ratio. power is then applied to the internal voltage refe rence. finally, power is appli ed to the d/a converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, vq. mode pin is: mode figure tied to vl i2s 7 tied to gnd left justified 8 tied to lrck right justified - 24 bit 9 tied to mclk right justified - 16bit 10 gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 11. de-emphasis curve (fs = 44.1khz)
cs4361 16 ds672a2 user: apply power wait state user: apply lrck and mclk mclk/lrck ratio detection user: applied sclk user: remove lrck or mclk user: change mclk/lrck ratio sclk mode = internal sclk mode = external normal operation de-emphasis available analog output is generated normal operation de-emphasis not available analog output is generated user: change mclk/lrck ratio user: apply rst user: remove lrck or mclk user: apply rst user: apply mclk, release rst power-down state vq and outputs low vq and outputs ramp down vq and outputs ramp down vq and outputs ramp up user: no sclk figure 12. cs4361 initializat ion and power-down sequence
cs4361 ds672a2 17 4.6 output transient control the cs4361 uses popguard ? technology to minimize the effects of output transients during power-up and power- down. when implemented with external dc-blocking capacitors connected in series with the audio outputs, this fea- ture eliminates the audio transients commonly produced by single-ended, sing le-supply converters. to make best use of this feature, it is nece ssary to understand its operation. 4.6.1 power-up when the device is initially powered-up, the audio output s, aout1-6 are clamped to vq which is initially low. after rst is released and mclk is applied, the outputs b egin to ramp with vq towards the nominal quiescent voltage. this ramp takes approximately 200 ms to comp lete. the gradual voltage ramping allows time for the external dc-blocking capacitors to charge to vq, effect ively blocking the quiescent dc voltage. audio output begins approximately 2000 sample periods after valid lrck and sdin are supplied (and sclk, if used). 4.6.2 power-down to prevent audio transients at power-down, the dc-blocki ng capacitors must fully discharge before turning off the power. in order to do this rst should be held low for a period of about 250 ms before removing power. dur- ing this time voltage on vq and the audio outputs dischar ge gradually to gnd. if power is removed before this 250 ms time period has passed a tran sient will occur when the va supply dr ops below that of vq. there is no minimum time for a power cycle, power may be re-applied at any time. when changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on sdin for at least 10 lrck samples before the change is made. during the clocking change the dac outputs will always be in a zero data state. if non-zero audio is present at th e time of switching, a slight click or pop may be heard as the dac output automatically goe s to its zero data state. 4.7 grounding and powe r supply decoupling as with any high resolution converter, the cs4361 requires careful attention to power supply and grounding arrange- ments to optimize performance. figure 6 shows the re commended power arrangement with va connected to a clean +3.3 v or +5 v supply. for best performance, decoupling and filter capacitors should be located as close to the de- vice package as possible, with the sm allest capacitors placed closest. 4.8 analog output and filtering the analog filter present in the cs4361 is a switched-capacitor filt er followed by a continu ous-time, low-pass filter. its response, combined with that of the digital interpolator, is given in figures 14 - 21. the recommended external analog circuitry is shown in the ?typical connection diagram? on page 11. the analog outputs are named aout1-6. the sdin1 feeds aout1 as the ?left? marked data and aout2 as the ?right? marked data. the sdin2 feeds aout3 as the ?left? marked data an d aout4 as the ?right? marked data. the sdin3 feeds aout5 as the ?left? marked data and aout6 as the ?right? marked data.
cs4361 18 ds672a2 4.9 mute control the mutec pin is intended to be used as control for an external mute circ uit in order to add off- chip mute capability. this pin becomes active unde r the following conditions. 1) during power-up initialization 2) upon reset 3) if the mclk to lrck ratio is incorrect 4) upon receipt of 8192 consecutive samples of zero 5) during power-down. the mutec pin will only go active on static zero data only if all 6 channels satisfy th e 8192 sample r equirement. if any channel receives non-zero data then the mute pin will return low (inactive). use of the mute control func tion is not mandatory but is recommended for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute cont rol function can enable the syst em designer to achieve idle channel noise & signal-to-noise ratios wh ich are only limited by the external mute circuit. the mutec pin is an ac- tive-high cmos driver. see figure 13 below for a suggested active-high mute circuit. 470 ? audio out 2 k ? 10 k ? -v +v a mmun2111lt1 aout mute c c s4361 ac couple 47 k ? 10 k ? filter cap mmun2211lt1 (if available) 6 6 (low r on ) figure 13. suggested active-low mute circuit
cs4361 ds672a2 19 5.parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to- noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distor tion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries asso ciation of japan , eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c.
cs4361 20 ds672a2 6.ordering informat ion 7.package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. model temperature package cs4361-czz -10 to +70 c 20-pin plastic tssop - lead-free CS4361-DZZ -40 to +85 c 20-pin plastic tssop - lead-free inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs4361 ds672a2 21 8.appendix figure 14. single speed stopband rejectio n figure 15. single speed transition band figure 16. single speed transition band figure 17. single speed passband ripple
cs4361 22 ds672a2 figure 18. double speed stopband reject ion figure 19. double speed transition band figure 20. double speed transition band figure 21. double speed passband ripple
cs4361 ds672a2 23 figure 22. quad speed stopband rejection f igure 23. quad speed transition band 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 amplitude (db) frequency(normalized to fs) figure 24. quad speed transition band figure 25. quad speed passband ripple 0.4 0.45 0.5 0.55 0.6 0.65 0.7 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) frequency(normalized to fs)

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